1. Field of the Invention
The present invention relates to an improvement in a semiconductor memory device and, more particularly, to a nonvolatile memory device in which potential variations of internal signal lines which are caused in reading out storage information from a memory cell are suppressed.
2. Description of the Related Art
A background art nonvolatile memory device proposed prior to the present invention has an internal circuit arrangement shown in, e.g., FIG. 5. Only memory cells required for descriptive convenience are illustrated in consideration of continuity of a large number of memory cells.
Referring to FIG. 5, reference numerals 21 denote word lines WLi, WLi+1, . . . ; 22, bit lines BLj, BLj+1, . . . ; and 24, memory cells Mij, Mij+1, Mi+1j . . . A memory cell incorporating at least one MOS transistor having source, drain, and gate electrodes is arranged at the intersection between each word line 21 and each bit line 22.
Memory cells 24 are arranged in a matrix form. The gate electrodes of the respective memory cells are connected to word lines 21 in units of rows. The drain and source electrodes of these memory cells are connected to bit lines 22 and virtual ground lines 23 represented by GLj, GLj+1, . . . in units of columns. Each bit line 22 is connected to corresponding pull-up circuit (constant voltage circuit) 26 through corresponding bias load MOS transistor 25 and set at a high potential level. These bit lines 22 are connected to sense amplifiers 28 represented by SAj, SAj+1, . . . through switching MOS transistors 27a controlled by selection signals Yj, Yj+1, . . . , respectively.
Each bias load MOS transistor 25 is set in a normally ON state because it is connected to reference voltage source 31. Each virtual ground line 23 is set in a bias or ground level through corresponding switching element (MOS transistor) 27b ON/OFF-controlled by selection signal Yj. Control signal S and control signal S* as the inverted signal of control signal S determine the potential level at which each virtual ground line 23 is set.
When potential line 29 connected to virtual ground line GLj is set at the ground level (or bias level) upon ON/OFF operations of switching elements S1 and S2 and switching elements S*1 and S*2 controlled by control signals S and S*, potential line 30 connected through switching element 27b to virtual ground line GLj+1 adjacent to virtual ground line GLj is set at the bias level (or ground level).
Data read access to programmed memory cells is performed by causing a sense amplifier to detect an ON state of the MOS transistor of each memory cell between the corresponding bit and virtual ground lines.
For example, assume that word line WLi is selected so as to turn on the gate of selection target memory cell Mij in memory cells arranged in the matrix form. Signal Yj is applied to turn on switching MOS transistors 27a and 27b respectively coupled to bit line (BLj) 22 and virtual ground line (GLj) 23 connected to the source and drain of memory cell Mij. When MOS transistor 27a is turned on, bit line BLj is connected to corresponding sense amplifier 28. When MOS transistor 27b is turned on, virtual ground line GLj is connected to potential line 29.
When the source-drain path of memory cell Mij is set in the ON state under the condition that the connection end potential between memory cell Mij and virtual ground line GLj is set at the ground level, the potential of bit line BLj changes to flow a current to this bit line. Sense amplifier 28 connected to bit line BLj can detect the ON state of memory cell Mij. At this time, if the source-drain path of memory cell Mij is set in an OFF state, the potential of bit line BLj does not change, and no current flows. Therefore, sense amplifier 28 can detect the OFF state of memory cell Mij. Upon detection of the ON/OFF state, information stored in memory cell Mij can be read out.
At this time, memory cell Mij+1 adjacent to memory cell Mij is arranged on the same word line as in memory cell Mij, memory cells Mij and Mij+1 are simultaneously selected. However, since virtual ground line GLj+1 is connected to common bias potential line 30 through switching element Sg2 and is set at the bias level, no potential difference occurs in the source-drain path of memory cell Mij+1. No current flows in this source-drain path regardless of the programmed state of cell Mij+1. Therefore, data read access to memory cell Mij will not be avoided.
In reading information from memory cell Mij+1 adjacent to memory cell Mij, control signals S and S* are switched to set virtual ground line GLj+1 to the ground level, and the same operations as described above are performed.
Data can be read out from memory cells Mij and Mij+1 in accordance with selection of word line WLi and switching operations of control signals S and S*. These operations are repeated to arbitrarily and continuously read out the program information stored in the memory cells.
The above description has exemplified a binary memory in which information stored in memory cells is binary data. The principle of operation is basically kept unchanged even in multi-value memories.
The nonvolatile memory device having the arrangement shown in FIG. 5 has the following problems.
(1) In reading out storage information from memory cell Mij, equivalent parallel capacitances C1 and C2 are generated in common potential lines 29 and 30 in accordance with the substrate-wiring parasitic capacitance of one virtual ground line GLj, the diffusion capacitances of switching elements Sg1, Sg2, S1, S2, S*1, and S*2, and the parasitic capacitances of common potential lines 29 and 30 themselves. In reading out memory information upon switching common potential lines 29 and 30 from the bias level to the ground level, and vice versa, it takes time to charge or discharge common potential lines 29 and 30 (equivalent capacitances C1 and C2). For this reason, bias charging to virtual ground line 23 (GLj . . . ) is delayed, and hence high-speed data read access to the memory device is impaired. In addition, equivalent capacitances C1 and C2 are charged/discharged every time information is read out. The power consumption of the memory device is increased by a current component caused by this charge/discharge operation. PA0 (2) Sense amplifier 28 is generally of a current detection type and normally includes a feedback circuit system. In this case, bias voltage source 20* is arranged by a feedback circuit system similar to that of sense amplifier 28. When such a feedback circuit system is included, overshooting or ringing may occur in the potential change of the common potential line due to the presence of equivalent capacitances C1 and C2 and the wiring inductance of the signal lines during abrupt charging of virtual ground line 23 to the bias level by bias voltage source 20*. When this overshooting or ringing has occurred, the potential of the common potential line is not converged to a desired bias level, but varies to interfere with the operational stability of the nonvolatile memory device. It also takes a long period of time to stabilize the bias level (or to eliminate overshooting or ringing). As a result, high-speed data read access is impaired. PA0 (3) Bias voltage source 20* in FIG. 5 requires to rapidly charge common potential line 29 or 30. For this reason, the internal circuit scale (i.e., a circuit area in an IC chip) is large and complicated, resulting in an increase in power consumption.
In particular, problems associated with the parasitic capacitances (C1 and C2) and the electrical characteristics of the feedback circuit system also vary depending on the manufacturing process of nonvolatile memory devices. Therefore, these problems are significant in view of product yields, manufacturing costs, and quality.